The Computer Organization & Design class I took at Iowa State was without a doubt the hardest lab-based class I have taken at Iowa State University. That is not to say that the material taught was difficult to learn, but that the labs were incredibly complex and required a lot of time and effort to complete.
This was the first class that I had taken where I used VHDL. We spent maybe two labs learning how to code in VHDL and then moved on to creating actual processor parts immediately. For the second half of this class, in groups of two, we built two fully functional 32-bit processors that were designed to implement 45 instructions out of the MIPS ISA. The first processor was a single-cycle processor, while the other was a pipelined processor. Personally I thought both were very hard to build, but some of the difficulty may have stemmed from the fact that I coded 80-90% of the projects.
Both of these processors were completely built from scratch with VHDL. The ALU was built by myself, which could shift, add, subtract, multiply, plus comparator & bitwise operators on both register values and an immediate. The processor also had a separate ALU that was used exclusively for conditional branches. I included a diagram of our completed processor below.
After building the single cycle processor, we moved on to breaking this processor up into modules that could be used with a pipeline processor. Our pipeline processor was fairly similar, with the addition of registers between each stage in the pipeline that would hold values. These registers were controlled with logic modules that would check for data hazards or stalls and make necessary adjustments if something was detected. Most of the data hazards that we needed to prevent came from forwarding data from later stages to earlier stages if a new value for a register address was needed for an operation. Due to the time needed to build the assignment and the project’s instructions, we were not able to implement forwarding and hazard detection for branching instructions, and would stall the processor instead. A simplified diagram for this module is given below.
Despite the difficulty of this class, I really enjoyed taking it and definitely would like to work with VHDL again in the future. It really felt good to have a working 32-bit pipeline processor at the end of the semester that my teammate and I built from the ground up. Even though these projects cost me many hours that I could have spent sleeping, I feel like building these processors was one of my greatest achievements at Iowa State.
Due to the fact that these projects are still being assigned at Iowa State, I’d prefer not to leave my code online. However, if you are not a student at Iowa State, feel free to contact me by any means if you’d like to see my code!